Most integrated circuits are designed to carry a given, relatively small amount of current. As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
When a current flow that is larger than that for which the integrated circuit is designed is passed through the circuit, the current flow tends to destroy various elements of the integrated circuit, such as gate dielectrics and junctions, rendering it either unstable or inoperable. One source of excessive current flow is called electrostatic discharge. Electrostatic discharge is a general condition where a charge imbalance builds up over a period of time, caused by one or more of a variety of conditions, and then is suddenly released. The current flow, although extremely brief, can be quite high. Electrostatic discharge is not an uncommon occurrence in circuits. If unaccounted for in the design of integrated circuits, electrostatic discharge can potentially be a major cause of failure for integrated circuits.
Various methods and structures for the shunting of electrostatic discharge have been proposed. With reference now to FIG. 1 there is depicted a circuit diagram 10 for a prior art grounded gate N channel MOSFET 12. Such a device is typically used for arresting electrostatic discharge in an integrated circuit. The MOSFET 12 has a source that is tied to a voltage source, such as a VDD, and a drain that is tied to a voltage ground, such as a VSS. The gate of the MOSFET 12 is also tied to the ground, through a resistor 14. With the gate coupled to ground in this manner, the circuit 10 is a type of GGNMOS, or grounded gate N type metal-oxide-semiconductor field effect transistor.
During what is commonly known as a snapback, the parasitic bipolar transistor associated with the NMOS will conduct a much higher current when the NMOS drain node reaches a trigger voltage, V_trigger. This high current causes a reduction of the drain voltage to the holding voltage, V_hold. This lowering of the holding voltage limits the voltage that is seen by the downstream functional device, thus protecting the downstream device from an electrostatic discharge. The parasitic capacitance associated with this GGNMOS 10 is usually around a few hundred femtofarads.
Unfortunately, this capacitance is unacceptably high for most high frequency and high speed applications. The problem with the circuit of FIG. 1 is that the nodal capacitance is higher than about one hundred femtofarads. Radio frequency and other high speed applications suffer performance degradations with this degree of capacitance, because the relatively high capacitance of the circuit slows its switching speed to an unacceptably low rate.
Radio frequency and higher speed applications demand parasitic capacitance of less than about one hundred femtofarads. Thus, although the electrostatic discharge handling performance of the circuit 10 depicted in FIG. 1 may be adequate, the circuit 10 cannot be used in high speed applications.
What is needed, therefore, is a system for handling electrostatic discharge in integrated circuits that overcomes problems such as those described above, at least in part.